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sram MT5C2561 austin semiconductor, inc. MT5C2561 rev. 2.5 1/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 features ? high speed: 35, 45, 55, and 70 ? battery backup: 2v data retention ? low power standby ? high-performance, low-power, cmos double-metal process ? single +5v ( +10%) power supply ? easy memory expansion with ce\ ? all inputs and outputs are ttl compatible options marking ? timing 35ns access -35 45ns access -45 55ns access -55* 70ns access -70* ? package(s) ceramic dip (300 mil) c no. 106 ceramic lcc ec no. 204 ? operating temperature ranges industrial (-40 o c to +85 o c) it military (-55 o c to +125 o c) xt ? 2v data retention/low power l *electrical characteristics identical to those provided for the 45ns access devices. pin assignment (top view) available as military specifications ? smd 5962-88725 ? smd 5962-88544 ? mil-std-883 24-pin dip (c) (300 mil) general description the austin semiconductor sram family employs high-speed, low-power cmos and are fabricated using double- layer metal, double-layer polysilicon technology. for flexibility in high-speed memory applications, austin semiconductor offers chip enable (ce\) on all organiza- tions. this enhancement can place the outputs in high-z for additional flexibility in system design. the x1 configuration features separate data input and output. writing to these devices is accomplished when write enable (we\) and ce\ inputs are both low. reading is accom- plished when we\ remains high and ce\ goes low. the device offers a reduced power standby mode when disabled. this allows system designs to achieve low standby power re- quirements. these devices operate from a single +5v power sup- ply and all inputs and outputs are fully ttl compatible. 256k x 1 sram sram memory array for more products and information please visit our web site at www.austinsemiconductor.com 28-pin lcc (ec) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 a6 a7 a8 a9 a10 a11 a14 a15 a0 q we\ vss vcc a5 a4 a3 a2 a1 a17 a16 a13 a12 d ce\ 3 2 1 28 27 13 14 15 16 17 4 5 6 7 8 9 10 11 12 26 25 24 23 22 21 20 19 18 nc a9 a10 a11 a14 a15 a0 q nc nc a4 a3 a2 a1 a17 a16 a13 nc a12 d ce\ vss we\ a8 a7 a6 vcc a17
sram MT5C2561 austin semiconductor, inc. MT5C2561 rev. 2.5 1/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 functional block diagram truth table row decoder 262,144-bit memory array i/o control v cc gnd d q ce\ we\ a13 a14 a15 a16 a17 a0 a1 a2 a3 a4 column decoder a5 a6 a7 a8 a9 a10 a11 a12 power down mode ce\ we\ dq power standby h x high-z standby read l h q active write l l high-z active
sram MT5C2561 austin semiconductor, inc. MT5C2561 rev. 2.5 1/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 absolute maximum ratings * *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. electrical characteristics and recommended dc operating conditions (-55 o c < t c < 125 o c; v cc = 5v +10%) capacitance voltage on any pin relative to vss..................................-0.5v to +7v voltage on vcc supply relative to vss.............................-0.5v to +7v voltage applied to q.........................................................-0.5v to +6v storage temperature......................................................-65 o c to +150 o c power dissipation..............................................................................1w short circuit output current.........................................................50ma lead temperature (soldering 10 seconds)....................................+260 o c junction temperature..................................................................+175 o c sym -35 -45 units notes i ccsp 120 120 ma 3 i cclp 100 100 ma 3 power supply current: standby i sbt1 25 25 ma i sbcsp 20 20 ma "l" version only i sbclp 33ma ce\ > v cc -0.2v; v cc = max v il < v ss +0.2v v ih > v cc -0.2v; f = 0 hz ce\ > v ih ; all other inputs < v il or > v ih , v cc = max f = 0 hz max conditions power supply current: operating parameter ce\ < v il ; v cc = max f = max = 1/t rc (min) output open description conditions sym min max units notes input high (logic 1) voltage v ih 2.2 v cc +0.5 v1 input low (logic 0) voltage v il -0.5 0.8 v 1, 2 input leakage current 0v< v in < v cc il i -10 10 a output leakage current output(s) disabled 0v< v out < v cc il o -10 10 a output high voltage i oh = -4.0ma v oh 2.4 v 1 output low voltage i ol = 8.0ma v ol 0.4 v 1 parameter conditions sym max units notes input capacitance c i 10 pf 4 output capacitance c o 12 pf 4 t a = 25 o c, f = 1mhz vcc = 5v
sram MT5C2561 austin semiconductor, inc. MT5C2561 rev. 2.5 1/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 electrical characteristics and recommended ac operating conditions (note 5) (-55 o c < t c < 125 o c; v cc = 5v +10%) min max min max units notes read cycle read cycle time t rc 35 45 ns address access time t aa 35 45 ns chip enable access time t ace 35 45 ns output hold from address change t oh 33ns chip enable to output in low-z t lzce 3 3 ns 7 chip disable to output in high-z t hzce 20 20 ns 6, 7 chip enable to power-up time t pu 0 0 ns 4 chip disable to power-down time t pd 35 45 ns 4 write cycle write cycle time t wc 35 45 ns chip enable to end of write t cw 30 40 ns address valid to end of write t aw 30 40 ns address setup time t as 00ns address hold from end of write t ah 55ns write pulse width t wp 30 40 ns data setup time t ds 20 20 ns data hold time t dh 00ns write disable to output in low-z t lzwe 0 0 ns 7 write enable to output in high-z t hzwe 0 15 0 20 ns 6, 7 -35 -45 description symbol
sram MT5C2561 austin semiconductor, inc. MT5C2561 rev. 2.5 1/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 ac test conditions input pulse levels ...................................... vss to 3.0v input rise and fall times ......................................... 5ns input timing reference levels ................................ 1.5v output reference levels ....................................... 1.5v output load ................................. see figures 1 and 2 notes 1. all voltages referenced to v ss (gnd). 2. -3v for pulse width < 20ns 3. i cc is dependent on output loading and cycle rates. the specified value applies with the outputs unloaded, and f = 1 hz. t rc (min) 4. this parameter is guaranteed but not tested. 5. test conditions as specified with the output loading as shown in fig. 1 unless otherwise noted. 6. t lzce , t lzwe , t lzoe , t hzce , t hzoe and t hzwe are specified with cl = 5pf as in fig. 2. transition is measured 200mv typical from steady state voltage, allowing for actual tester rc time constant. 7. at any given temperature and voltage condition, t hzce is less than t lzce , and t hzwe is less than t lzwe and t hzoe is less than t lzoe . 8. we\ is high for read cycle. 9. device is continuously selected. chip enable is held in its active state. 10. address valid prior to, or coincident with, latest occurring chip enable. 11. t rc = read cycle time. 12. chip enable (ce\) and write enable (we\) can initiate and terminate a write cycle. fig. 1 output load equivalent fig. 2 output load equivalent data retention electrical characteristics (l version only) 123 1 2 3 1 2 3 123 1 23 4 1 23 4 1 23 4 1234 dont care undefined low vcc data retention waveform v th = 1.73v q 167 w 30pf v th = 1.73v q 167 w 5pf 12345678 12345678 12345678 12345678 123 1 2 3 1 2 3 123 1234 1 23 4 1 23 4 1234 123456789 123456789 123456789 123456789 123 1 2 3 1 2 3 123 1234 1 23 4 1 23 4 1234 data retention mode v dr > 2v 4.5v 4.5v v dr t cdr t r v ih v il v cc ce\ description conditions sym min max units notes vcc for retention data v dr 2 --- v data retention current ce\ > (v cc - 0.2v) v in > (v cc - 0.2v) or < 0.2v v cc = 2v i ccdr 900 m a chip deselect to data retention time t cdr 0 --- ns 4 operation recovery time t r t rc ns 4, 11
sram MT5C2561 austin semiconductor, inc. MT5C2561 rev. 2.5 1/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 taa toh trc trc previous data valid valid data valid address dq read cycle no. 1 8, 9 t rc t aa t oh trc trc ce\ read cycle no. 2 7, 8, 10 t rc tpd tpu thzce tace tlzce data valid dq icc t hzce t lzce t ace t pu t pd
sram MT5C2561 austin semiconductor, inc. MT5C2561 rev. 2.5 1/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 note: output enable (oe\) is inactive (high). write cycle no. 2 7, 12 (write enabled controlled) write cycle no. 1 12 (chip enabled controlled) tdh tds twp1 twp1 tah tcw taw tcw tas twc twc high z data vaild address ce\ we\ d q t wc t aw t as t cw t ah t wp t ds t dh 123456789012345678901 123456789012345678901 1 1 1 1 1 123456789012345678901234567890121234567890 123456789012345678901234567890121234567890 1 1 1 1 1 tdh twp1 twp1 tas taw tcw tah tcw twc twc data valid address ce\ we\ d q high-z t dh t ds t wc t aw t ah t cw t as t wp 1234 1234 1234 1234 1234567890123456 1 23456789012345 6 1 23456789012345 6 1234567890123456 1 1 1 1 1234 1234 1234 1234 123456 1 2345 6 1 2345 6 123456 12 12 12 12 1 1 1 1 1 1 1 1 12345678901234567 1 234567890123456 7 12345678901234567 12 12 12 12 12 1 1 12345678901234567890123 1 234567890123456789012 3 12345678901234567890123 12 1 1 1 1 123456789 123456789 123456789 t hzwe t lzwe 123 1 23 123 1234 1 23 4 1 23 4 1234 dont care undefined
sram MT5C2561 austin semiconductor, inc. MT5C2561 rev. 2.5 1/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 mechanical definitions* asi case #106 (package designator c) smd #5962-88544 & #5962-88725, case outline l *all measurements are in inches. d pin 1 note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. min max a --- 0.200 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d --- 1.280 e 0.220 0.310 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 --- symbol 0.100 bsc smd specifications 0.300 bsc e b b2 a q l s1 c note e 0 o to 15 o ea
sram MT5C2561 austin semiconductor, inc. MT5C2561 rev. 2.5 1/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 mechanical definitions* asi case #204 (package designator ec) smd# 5962-88544, case outline x *all measurements are in inches. note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. a a1 d3 min max a 0.060 0.120 a1 0.050 0.088 b1 0.022 0.028 b2 d 0.342 0.358 d1 d2 d3 --- 0.358 e 0.540 0.560 e1 e2 e3 --- 0.558 e h l 0.045 0.055 l2 0.075 0.095 0.100 bsc 0.040 ref 0.050 bsc 0.200 bsc 0.400 bsc symbol smd specifications 0.072 ref 0.200 bsc e d e3 hx45 o e1 l2 b1 d1 l e b2 e2 d2 h x 45 o
sram MT5C2561 austin semiconductor, inc. MT5C2561 rev. 2.5 1/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 *available processes it = industrial temperature range -40 o c to +85 o c xt = extended temperature range -55 o c to +125 o c 883c = full military processing -55 o c to +125 o c ** options l = 2v data retention/low power ordering information example: MT5C2561ec-70/xt device number package type speed ns options** process device number package type speed ns options** process MT5C2561 c -35 l /* MT5C2561 ec -35 l /* MT5C2561 c -45 l /* MT5C2561 ec -45 l /* MT5C2561 c -55 l /* MT5C2561 ec -55 l /* MT5C2561 c -70 l /* MT5C2561 ec -70 l /* example: MT5C2561c-45l/it
sram MT5C2561 austin semiconductor, inc. MT5C2561 rev. 2.5 1/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 asi to dscc part number cross reference* asi package designator ec asi part # smd part # MT5C2561ec-35/883c 5962-8872501xx MT5C2561ec-45/883c 5962-8872502xx MT5C2561ec-55/883c 5962-8872503xx MT5C2561ec-70/883c 5962-8872504xx MT5C2561ec-35l883c 5962-8854401xx MT5C2561ec-45l883c 5962-8854402xx MT5C2561ec-55l883c 5962-8854403xx MT5C2561ec-70l883c 5962-8854404xx asi package designator c asi part # smd part # MT5C2561c-35/883c 5962-8872501lx MT5C2561c-45/883c 5962-8872502lx MT5C2561c-55/883c 5962-8872503lx MT5C2561c-70/883c 5962-8872504lx MT5C2561c-35l883c 5962-8854401lx MT5C2561c-45l883c 5962-8854402lx MT5C2561c-55l883c 5962-8854403lx MT5C2561c-70l883c 5962-8854404lx * asi part number is for reference only. orders received referencing the smd part number will be processed per the smd.

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